The present invention relates to electronic circuits, and, more particularly, to an electronic device for controlling the bouncing or oscillating of an output signal about its final value in an integrated electronic circuit.
The invention relates particularly, but not exclusively, to an electronic device for controlling the switching of an output of a CMOS electronic circuit integrated on a semiconductor substrate. The electronic device includes at least one MOS transistor output stage for driving an external load.
Bouncing appears in integrated electronic circuits as certain digital output signals switch between two logic states. Bouncing is the transient decaying oscillations about a final value. These integrated circuits include a final output stage for each circuit output, which are essentially an interface circuit for driving an external load.
The current design of integrated circuits operating at a low voltage requires an ever larger drive current I (e.g., 24 mA to 48 mA per output) for the external loads. The variation of this current during switching of the output signal induces a voltage which follows the equation V=LdI/dt. This is due to the presence of inductive components L, which are attributable to parasitic inductances in the package itself and to the connecting cables. A typical value of this induced voltage would be around 500 mV.
The significance of this voltage increases as several outputs are switched simultaneously in the integrated electronic circuit. This is due to the induced voltage at that output, which will affect the voltages at one or more of the adjacent outputs. The induced voltage at the output occurs when one output of the integrated circuit switches over. Then, after the outputs have switched over, the output voltage will be oscillating about its final value, i.e., bouncing, before it becomes settled at a voltage value corresponding to a high or a low logic state.
One method of minimizing this induced voltage includes controlling the leading edge of the drive voltage, that is, the slew rate of the integrated circuit output stage. A first approach includes dividing each final output stage into a plurality of parallel stages, wherein all the stages are identical. These stages include active circuitry whereby the individual stages can be turned on sequentially. Thus, the switching edge of the current becomes offset or stepped, and the current variation can be much smaller. While being advantageous, this first approach has drawbacks, such as the control circuitry being quite complicated for these stages.
A second approach is described in European Patent Application No. 678983. This application is incorporated herein by reference in its entirety, and is assigned to the assignee of the present invention. A circuit is disclosed in the application in which a current generator is used for controlling the leading edge of the drive current. Although achieving its objective, this second approach also involves a circuit arrangement which is fairly complicated and expensive to manufacture.
In view of the foregoing background, it is an object of the present invention to provide a final stage for an integrated circuit which is easily implemented and has structural and functional features for providing improved control of the output signal leading edges, thereby overcoming the limitations and drawbacks of prior art output stages.
This and other objects, features and advantages are provided by an output stage of an electronic device comprising a MOS transistor having a plurality of gate regions of different lengths for turning on the device sections.
More particularly, the electronic device may comprise a semiconductor substrate, and at least one output stage on the semiconductor substrate. The output stage may compromise at least on output transistor for providing an output voltage to an external load connected thereto. The output transistor preferably comprises a plurality of transitor legs connected in parallel, with each transistor leg comprising a transistor having a channel defined therein.
A length of each respective channel is preferably different from a length of other channels among the plurality of transistors legs, and each transistor leg is preferably individually turned on and at different times for controlling oscillation of the output voltage about a final value.
The output stage preferably comprises a CMOS inverting stage, and the at least on transistor preferably comprises a pair of transistors connected in series. A first transistor of the pair of transistors connected to a first voltage reference, and a second transistor of the pair of transistors may be connected to a second voltage reference.
The pair of transistors preferably comprises a pull-up transistor and a pull-down transistor, wherein the pull-up transistor comprises an p-type transistor and pull-down transistor comprises an N-type transistor. The different channel lengths for the plurality of transistor legs preferably have increasing lengths, wherein the lengths increase within a range of about 0.3 mm to 0.6 mm. The plurality of transistor legs preferably have the same channel width.